Memory cells of a dynamic random access memory (DRAM) generally comprise a storage capacitor for storing an electrical charge which represents an information to be stored, and an access transistor connected with the storage capacitor. The access transistor comprises a first and a second source/drain regions, a channel connecting the first and second source/drain regions and a gate electrode controlling an electrical current flowing between the first and second source/drain regions. The transistor is usually at least partially formed in a semiconductor substrate. The information stored in the storage capacitor is read out or written in by addressing the access transistor via the corresponding word line. In particular, the information is read out to a corresponding bit line via a bit line contact.
There is a lower boundary of the channel length of the access transistor, below which the isolation properties of the access transistor in a non-addressed state are not sufficient. The lower boundary of the effective channel length Leff limits the scalability of planar transistor cells with an access transistor, formed horizontally with respect to the substrate surface of the semiconductor substrate.
Vertical transistor cells offer a possibility of enhancing the channel length while maintaining the surface area necessary for forming the memory cell. In such a vertical transistor cell the source/drain regions of the access transistor and the channel region are arranged in a direction perpendicular to the substrate surface. One of the problems involved with such a vertical transistor cell is the difficulty in providing a surface contact to a stacked capacitor. Accordingly, such a vertical transistor is difficult to integrate with a stacked capacitor.
Enhancing the effective channel length Leff by a recessed channel transistor is known. In such a transistor, the first and second source/drain regions are arranged in a horizontal plane parallel to the substrate surface. The gate electrode is arranged in a recess groove, which is disposed between the two source/drain regions of the transistor in the semiconductor substrate. Accordingly, the effective channel length equals to the sum of the distance between the two source/drain regions and the two fold of the depth of the recess groove. The effective channel width Weff corresponds to the nominal structural size F.
It is also known that a memory cell array has transistors formed in continuous active area lines. The active area lines are arranged in parallel with the bit lines. In particular, the gate electrodes of the transistors from part from the word lines and the word lines including the gate electrodes are implemented as buried word lines.
Further, it is know that a transistor is formed in an active area with the form of a ridge, where two gate electrodes each form part of a corresponding word lines and disposed along the lateral sides of the active area. The active area is recessed at a channel portion of the transistor.
An improved memory cell array and method of forming such a memory cell array are desirable.